(1) Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device in which a bipolar transistor is formed on an insulating substrate having an SOI (Silicon-On-Insulator) structure. Further, the present invention is concerned with a method of producing such a semiconductor device.
(2) Background of the Invention
An insulating substrate is known in which two silicon substrates are bonded through an oxide film. There is also known a SIMOX substrate in which oxide ions are introduced from a surface of a silicon substrate and an oxide area having a predetermined depth from the surface is formed. These SOI substrates are suitable for producing low-parasitic capacitance and high-speed semiconductor elements in which semiconductor elements are formed in a surface area thereof and isolated from a peripheral area by a dielectric layer. Recent technical advance makes it possible to produce a submicron silicon active layer formed on an oxide film of the SOI substrate. By using such an SOI substrate, it is possible to produce a MOS (Metal Oxide Semiconductor) transistor which has a high transconductance (gm) and a suppressed short channel effect. However, in order to improve a load driving ability, it is desired that a bipolar transistor be produced. A conventional bipolar transistor has a vertical structure in which current is vertically passed. At present, it is difficult to produce a vertical transistor using the SOI substrate. More specifically, a large number of production steps is needed, and it is particularly difficult to form a collector buried layer. For these reasons, there has been considerable activity in the development of producing a bipolar transistor having a lateral structure.
FIG. 1 shows a conventional lateral bipolar transistor having the SOI structure. A semiconductor layer 50 is formed on a semiconductor substrate 51 made of oxide silicon (SiO.sub.2). The semiconductor layer 50 has a p-type impurity concentration suitable for forming a p-type base region 52. A portion of the semiconductor layer 50 other than an element formation area thereof is oxidized, so that an element isolation region 55 is formed. The element formation region surrounded by the element isolation region 55 is selectively doped with an n-type impurity, so that an n-type emitter region 53 and an n-type collector region 54 are formed. An insulating layer 57 made of, for example, SiO.sub.2, is formed on the semiconductor layer 50, and openings are formed at predetermined positions of the semiconductor layer 50. Via these openings, an n.sup.+ -type polysilicon electrodes 62 and 63 which are in contact with predetermined semiconductor regions are formed. Similarly, an insulating film 58 made of, for example, SiO.sub.2, is formed. After an opening positioned above the p-type opening is formed in the insulating film 58, a p.sup.+ -type polysilicon electrode 61 is formed.
In the structure shown in FIG. 1, the polysilicon electrode 61 forms a base lead electrode, the polysilicon electrode 62 forms an emitter lead electrode, and the polysilicon electrode 63 forms a collector lead electrode. These polysilicon electrodes 61, 62 and 63 are isolated from each other by insulating layers 57, 58 and 59 respectively made of an insulating material, such as oxide silicon. Opening are formed in predetermined areas of the insulating layer 59. Via the openings, a base electrode 64, an emitter electrode 65 and a collector electrode 66 are formed, as shown in FIG. 1. The base electrode 64 is in contact with the polysilicon base lead electrode 61, and the emitter electrode 65 is in contact with the polysilicon emitter lead electrode 62. The collector electrode 66 is in contact with the polysilicon collector lead electrode 63.
The emitter region 53 and the collector region 54 are formed by diffusing the impurity ions from the surface of the p-type layer 50. In this case, the distance between the edge of the emitter region 53 and the edge of the collector region 54 increases as the distance from the surfaces of the regions increases. That is, the width of the base region 52 in the lateral direction (base width) increases as the depth increases.
The p-type base region 52 must have a lateral length equal to or greater than a predetermined length in the lateral direction. For example, the lateral width of the base region 52 is limited to 0.1-0.15 .mu.m. However, it is desired that the base region has a narrow and constant width in the depth direction thereof.